27 lines
1.5 KiB
Markdown
27 lines
1.5 KiB
Markdown
|
|
||
|
|
# *S*erial *P*eripheral *I*nterface
|
||
|
|
|
||
|
|
The SPI bus consists of a master device and one or more slave devices. The master device initiates the communication and controls the timing of data transfers, while the slave devices respond to the master's commands. Normally SPI uses four main cables for communication:
|
||
|
|
|
||
|
|
* SCLK (Serial Clock): This line carries clock signals generated by the master device. It synchronizes data transfer between the master and slaves.
|
||
|
|
|
||
|
|
* MOSI (Master Output/Slave Input): This line is used by the master to send data to the slave devices.
|
||
|
|
|
||
|
|
* MISO (Master Input/Slave Output): This line is used by the slave devices to send data back to the master.
|
||
|
|
|
||
|
|
* SS (Slave Select): Each slave device on the bus has its own SS line. The master uses these lines to select the specific slave device it wants to communicate with.
|
||
|
|
|
||
|
|
**Data Transfer**
|
||
|
|
The master device initiates the data transfer by selecting a slave device through its corresponding SS line. It then sends clock pulses on the SCLK line. On each clock pulse, the master sends a bit of data on the MOSI line, and the selected slave reads it on the MISO line. The data is typically transmitted in a specific order, such as most significant bit (MSB) first or least significant bit (LSB) first.
|
||
|
|
|
||
|
|
```mermaid
|
||
|
|
graph LR
|
||
|
|
style A fill:#6FB7FF,stroke:#333,stroke-width:2px
|
||
|
|
style B fill:#FFB86F,stroke:#333,stroke-width:2px
|
||
|
|
|
||
|
|
A(Master) -->|SCLK| B(Slave)
|
||
|
|
A -->|MOSI| B
|
||
|
|
B -->|MISO| A
|
||
|
|
A -->|SS| B
|
||
|
|
|
||
|
|
```
|